1. Field of the Invention
The present invention is generally in the field of semiconductor circuits. More particularly, the present invention is in the field of low noise amplifiers.
2. Related Art
Consumers continue to demand increased performance and lower cost from wireless communication devices, such as cell phones and Bluetooth-enabled transceivers. To meet this demand, manufacturers are faced with the challenge of increasing the performance of the various circuits in the wireless communication devices, while reducing the cost of those circuits. For example, wireless communication device manufacturers are challenged to provide low noise amplifiers (LNA) to meet high performance criteria, such as high gain, low noise, and high linearity, in the receivers of wireless communication devices at reduced cost.
In an attempt to meet the above LNA high performance criteria, manufacturers have provided an LNA having one transistor in a single stage circuit configuration. Although silicon-germanium (SiGe), gallium-arsenide (GaAs), and indium-phosphite (InP) technologies have been utilized to fabricate a heterojunction bipolar transistor (HBT) and/or a Field Effect Transistor (FET) for the single stage LNA, GaAs and InP HBTs have been more successful in meeting high performance criteria. However, HBTs/FETs utilizing GaAs or InP technologies are more expensive to fabricate than HBTs utilizing SiGe BiCMOS technology.
In another attempt to meet the above desired LNA performance criteria, manufacturers have provided an LNA utilizing a dual stage, two transistor circuit configuration. However, conventional dual stage, two transistor LNAs typically suffer from various performance limitations. For example, an LNA utilizing two SiGe HBTs in a cascode configuration exhibits undesirable high noise and/or poor linearity. By way of another example, an LNA utilizing a FET in both the input and output stages of a conventional dual stage cascode configuration exhibits undesirable high noise and low gain.
In a further attempt to meet the above LNA performance criteria, manufacturers have provided a dual stage LNA having two transistors, such as two SiGe HBTs, coupled in a cascade configuration. For example, in a cascade configuration, the collector of the first SiGe HBT can be coupled to the base of the second SiGe HBT, and the emitters of both SiGe HBTs can be connected to ground. As a result of having to provide bias current to each SiGe HBT, the dual stage LNA utilizing two transistors in a cascade configuration suffers from a high bias current requirement. Additionally, dual stage cascade LNA configuration suffers from high noise and/or poor linearity.
FIG. 1A shows a schematic diagram of an exemplary conventional single stage LNA. Single stage LNA 100 comprises transistor 102, which can be, for example, a SiGe, GaAs, or InP HBT. The base of transistor 102 may be coupled to a radio frequency (RF) signal in a wireless communication device. The RF signal can be amplified by transistor 102 and outputted at the collector of transistor 102. The collector of transistor 102 is also coupled to a bias load, and the emitter of transistor 102 is connected to ground.
A single stage LNA, such as single stage LNA 100, exhibits undesirable low gain and poor linearity performance characteristics under low bias current when utilizing a SiGe HBT. As discussed above, although a single stage LNA might provide better performance criteria when utilizing GaAs or InP technology, GaAs or InP technology is much more expensive than SiGe BiCMOS technology.
FIG. 1B shows a schematic diagram of an exemplary conventional bipolar cascode LNA. Bipolar cascode LNA 150 includes bipolar transistor 152 and bipolar transistor 154 coupled together in a cascode configuration. Bipolar transistors 152 and 154 can be, for example, SiGe HBTs. The base of bipolar transistor 152 may be coupled to an RF signal in a wireless communication device. The emitter of bipolar transistor 152 is connected to ground, and the collector of bipolar transistor 152 is coupled to the emitter of bipolar transistor 154.
The RF signal that is inputted at the base of bipolar transistor 152 is amplified by bipolar transistors 152 and 154 and outputted at the collector of bipolar transistor 154. The collector of bipolar transistor 154 is also coupled to a bias load. As discussed above, a conventional LNA comprising two bipolar transistors in a cascode configuration, such as bipolar cascode LNA 150, suffers from low linearity.
FIG. 1C shows a schematic diagram of an exemplary conventional FET cascode LNA. FET cascode LNA 170 includes FET 172 and FET 174 coupled together in a cascode configuration. For example, both FET 172 and FET 174 can be NFETs. The gate of FET 172 may be coupled to an RF signal in a wireless communication device. The source of FET 172 is connected to ground, and the drain of FET 172 is coupled to the source of FET 174. The RF signal is inputted at the gate of FET 172 is amplified by FET 172 and FET 174 and outputted at the drain of FET 174. The drain of FET 174 is also coupled to a bias load. As discussed above, a conventional LNA comprising two FETs in a cascode configuration, such as FET cascode LNA 170, suffers from high noise and low gain.
Thus, there is a need in the art for a low-cost LNA having high gain, high linearity, and low noise at low bias current.
The present invention is directed to a high performance BiFET low noise amplifier. The invention overcomes the need in the art for a low-cost low noise amplifier having high gain, high linearity, and low noise at low bias current.
According to one exemplary embodiment, a circuit comprises a bipolar transistor having a base, an emitter, and a collector. For example, the bipolar transistor can be an NPN SiGe HBT. The base of the bipolar transistor is also an input of the circuit. A received RF signal, for example, may be coupled to the input of the circuit via a capacitor. The emitter of the bipolar transistor is coupled to a first reference voltage, which may be, for example, a ground voltage. The emitter of the bipolar transistor, for example, may be coupled to the first reference voltage through a first impedance circuit. The first impedance circuit may be an inductor, for example.
According to this exemplary embodiment, the circuit further comprises a field effect transistor having a gate, a source, and a drain. For example, the field effect transistor may be an NFET. The collector of the bipolar transistor is coupled to the source of the field effect transistor. For example, the bipolar transistor may be coupled to the field effect transistor in a cascode configuration in a BiFET low noise amplifier. The gate of the field effect transistor is coupled to a bias voltage.
The drain of the field effect transistor is coupled to a second reference voltage, which may be, for example, the power supply voltage, which is also referred to as Vdd or Vcc in circuit design terminology. The drain of the field effect transistor is also an output of the circuit. The drain of the field effect transistor may be coupled to the second reference voltage through a second impedance circuit. The second impedance circuit may comprise an inductor and a capacitor. The inductor, for example, may couple the drain of the field effect transistor to the second reference voltage. The capacitor, for example, may couple the drain of the field effect transistor to an output load.